AC82G41SLGQ3 Datasheet, PDF (39/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Signal Description
2.2
2.2.1
System Memory (DDR2/DDR3) Interface Signals
System Memory Channel A Interface Signals
Signal Name
DDR_A_CK
DDR_A_CKB
DDR_A_CSB_[3:0]
Type
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
Description
SDRAM Differential Clocks:
• DDR2: Three per DIMM
• DDR3: Two per DIMM
SDRAM Inverted Differential Clocks:
• DDR2: Three per DIMM
• DDR3: Two per DIMM
DDR2/DDR3 Device Rank 3, 2, and 0 Chip Selects
DDR_A_CKE_[3:0]
O
DDR2/DDR3 Clock Enable:
SSTL-1.8/1.5 (1 per Device Rank)
DDR_A_ODT_[3:0]
DDR_A_MA_[14:0]
DDR_A_BS_[2:0]
DDR_A_RASB
DDR_A_CASB
DDR_A_WEB
DDR_A_DQ_[63:0]
DDR_A_DM_[7:0]
DDR_A_DQS_[7:0]
DDR_A_DQSB_[7:0]
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
I/O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
I/O
SSTL-1.8/1.5
I/O
SSTL-1.8/1.5
DDR2/DDR3 On Die Termination:
(1 per Device Rank)
DDR2 Address Signals [14:0]
DDR2/DDR3 Bank Select
DDR2/DDR3 Row Address Select signal
DDR2/DDR3 Column Address Select signal
DDR2/DDR3 Write Enable signal
DDR2/DDR3 Data Lines
DDR2/DDR3 Data Mask
DDR2/DDR3 Data Strobes
DDR2/DDR3 Data Strobe Complements
Datasheet
39