AC82G41SLGQ3 Datasheet, PDF (71/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
Table 10.
SMM Control Table
G_SMRAME D_LCK
0
x
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
D_CLS
X
X
0
0
1
1
X
0
1
D_OPEN
x
0
0
1
0
1
x
x
x
Processor
in SMM
Mode
x
0
1
x
1
x
0
1
1
SMM Code
Access
Disable
Disable
Enable
Enable
Enable
Invalid
Disable
Enable
Enable
SMM Data
Access
Disable
Disable
Enable
Enable
Disable
Invalid
Disable
Enable
Disable
3.8.5
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI Interface
originated transactions are not allowed to SMM space.
3.8.6
3.8.7
Processor WB Transaction to an Enabled SMM Address
Space
Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space must
be written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
SMM Access Through GTT TLB (Intel^® 82Q45, 82Q43,
82B43, 82G45, 82G43, 82G41 GMCH Only)
Accesses through GTT TLB address translation to enabled SMM DRAM space are not
allowed. Writes will be routed to Memory address 000C_0000h with byte enables de-
asserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB
translated address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through GMADR range will be snooped.
Assesses to GMADR linear range (defined via fence registers) are supported. PCI
Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when
translated, the resulting physical address is to enabled SMM DRAM space, the request
will be remapped to address 000C_0000h with de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
Datasheet
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