AC82G41SLGQ3 Datasheet, PDF (257/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Bit
14:12
11:10
9:4
3:0
Access
RO
RWO
RO
RO
Default
Value
100b
11b
10h
2h
RST/
PWR
Core
Core
Core
Core
Description
Reserved
Active State Link PM Support (ASLPMS): The MCH supports ASPM
L1.
Max Link Width (MLW): Indicates the maximum number of lanes
supported for this link.
10h = x16
Max Link Speed (MLS): Supported Link Speed - This field indicates
the supported Link speed(s) of the associated Port.
0001b = 2.5GT/s Link speed supported
0010b = 5.0GT/s and 2.5GT/s Link speeds supported
All other encodings are reserved.
8.39
LCTL—Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
B0–B1h
0000h
RO, RW, RW/SC
16 bits
This register allows control of PCI Express link.
Bit
15:12
11
10
9
Access
RO
Default
Value
0000000b
RW
0b
RW
0b
R0
0b
RST/
PWR
Core
Core
Core
Core
Description
Reserved
Link Autonomous Bandwidth Interrupt Enable: When Set,
this bit enables the generation of an interrupt to indicate that the
Link Autonomous Bandwidth Status bit has been set.
This bit is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification
capability must hardwire this bit to 0b.
Link Bandwidth Management Interrupt Enable: When Set,
this bit enables the generation of an interrupt to indicate that the
Link Bandwidth Management Status bit has been set.
This bit is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Hardware Autonomous Width Disable: When Set, this bit
disables hardware from changing the Link width for reasons other
than attempting to correct unreliable Link operation by reducing
Link width.
Devices that do not implement the ability autonomously to change
Link width are permitted to hardwire this bit to 0b.
The MCH does not support autonomous width change. So, this bit
is "RO".
Datasheet
257