AC82G41SLGQ3 Datasheet, PDF (170/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.3.2
EPLE1D—EP Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
50-53h
01000000h
RO, R/WO
32 bits
This register provides the first part of a Link Entry, which declares an internal link to
another Root Complex Element.
Bit
31:24
23:16
15:2
1
0
5.3.3
Access
RO
R/WO
RO
RO
R/WO
Default
Value
01h
00h
0000h
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Target Port Number (TPN): This field specifies the port
number associated with the element targeted by this link
entry (DMI). The target port number is with respect to the
component that contains this element as specified by the
target component ID.
Target Component ID (TCID): This field identifies the
physical or logical component that is targeted by this link
entry.
Reserved
Link Type (LTYP): This bit indicates that the link points to
memory-mapped space (for RCRB). The link address
specifies the 64-bit base address of the target RCRB.
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
EPLE1A—EP Link Entry 1 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
58-5Fh
0000000000000000h
RO, R/WO
64 bits
This register provides the second part of a Link Entry, which declares an internal link to
another Root Complex Element.
Bit
63:36
35:12
11:0
Access
RO
R/WO
RO
Default
Value
0000000h
000000h
000h
RST/PWR
Description
Core
Core
Core
Reserved: Reserved for Link Address high order bits.
Link Address (LA): This field contains the memory
mapped base address of the RCRB that is the target
element (DMI) for this link entry.
Reserved
170
Datasheet