AC82G41SLGQ3 Datasheet, PDF (162/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.44
TSTTP—Thermal Sensor Temperature Trip Point
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CDC-CDFh
00000000h
RO, R/W, R/W/L
32 bits
This register:
1. Sets the target values for the trip points in thermometer mode. See also TST
[Direct DAC Connect Test Enable].
2. Reports the relative thermal sensor temperature
All bits in this register are reset to their defaults by MPWROK.
Bit
Access
31:24
RO
23:16
R/W
15:8
R/W/L
7:0
R/W/L
Default
Value
00h
00h
00h
00h
RST/PWR
Description
Core
Core
Core
Core
Relative Temperature (RELT): In Thermometer mode,
the RELT field of this register report the relative
temperature of the thermal sensor. Provides a two's
complement value of the thermal sensor relative to the Hot
Trip Point. Temperature above the Hot Trip Point will be
positive.
TR and HTPS can both vary between 0 and 255. But RELT
will be clipped between ±127 to keep it an 8 bit number.
See also TSS[Thermometer mode Output Valid]
In the Analog mode, the RELT field reports HTPS value.
Aux0 Trip point setting (A0TPS): This field sets the
target for the Aux0 trip point.
Hot Trip Point Setting (HTPS): This field sets the target
value for the Hot trip point.
Lockable via TCO bit 7.
Catastrophic Trip Point Setting (CTPS): This field sets
the target for the Catastrophic trip point. See also
TST[Direct DAC Connect Test Enable].
Lockable via TCO bit 7.
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Datasheet