AC82G41SLGQ3 Datasheet, PDF (455/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2 DMI VC1 Remap Engine Registers
Table 27.
DMI VC1 Remap Engine Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
0–3h
8–Fh
10–17h
18–1Bh
1C–1Fh
20–27h
28–2Fh
34–37h
38–3Bh
3C–3Fh
40–43h
44–h
58–5Fh
64–67h
68–6Bh
6C–6Fh
70–77h
78–7Fh
100–107h
108–10Fh
200–20Fh
VER_REG
CAP_REG
ECAP_REG
GCMD_REG
GSTS_REG
RTADDR_REG
CCMD_REG
Version Register
00000010h
Capability Register
00C9008020
E30272h
Extended Capability Register
0000000000
001000h
Global Command Register
00000000h
Global Status Register
00000000h
Root-Entry Table Address Register
0000000000
000000h
Context Command Register
0000000000
000000h
FSTS_REG Fault Status Register
00000000h
FECTL_REG Fault Event Control Register
80000000h
FEDATA_REG Fault Event Data Register
00000000h
FEADDR_REG Fault Event Address Register
00000000h
FEUADDR_REG
Fault Event Upper Address
Register
00000000h
AFLOG_REG Advanced Fault Log Register
0000000000
000000h
PMEN_REG Protected Memory Enable Register 00000000h
PLMBASE_REG
Protected Low-Memory Base
Register
00000000h
PLMLIMIT_REG
Protected Low-Memory Limit
Register
00000000h
PHMBASE_REG
Protected High-Memory Base
Register
0000000000
000000h
PHMLIMIT_RE Protected High-Memory Limit
G
Register
0000000000
000000h
IVA_REG
Invalidate Address Register
0000000000
000000h
IOTLB_REG IOTLB Invalidate Register
0000000000
000000h
FRCD_REG Fault Recording Registers
0000000000
0000000000
0000000000
00h
RO
RO
RO
RO, W
RO
R/W, RO
RO, R/W, W
RO, RO/P,
R/WC/P
RO, R/W
RO, R/W
R/W, RO
RO
RO
RO, R/W
R/W, RO
R/W, RO
R/W, RO
RO, R/W
W, RO
R/W, RO
RO, RO/P,
R/WC/P
Datasheet
455