AC82G41SLGQ3 Datasheet, PDF (70/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
Table 8.
3.8.2
3.8.3
Table 9.
3.8.4
Transaction Address Ranges – Compatible, High, and TSEG
SMM Space Enabled
Compatible
High
TSEG
Transaction Address Space
000A_0000h to 000B_FFFFh
FEDA_0000h to FEDB_FFFFh
(TOLUD–STOLEN–TSEG) to
TOLUD–STOLEN
DRAM Space (DRAM)
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD–STOLEN–TSEG) to
TOLUD–STOLEN
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are
unpredictable and may cause the system to hang:
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI Interface, and
PCI-Express, and graphics devices). This is a BIOS responsibility.
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
5. Any address translated through the GMADR TLB must not target DRAM from
A_0000-F_FFFF.
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1), the Compatible
SMM space is effectively disabled. Processor-originated accesses to the Compatible
SMM space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP),
otherwise they are forwarded to the DMI Interface. PCI Express and DMI Interface
originated accesses are never allowed to access SMM space.
SMM Space Table
Global Enable High Enable TSEG Enable
G_SMRAME H_SMRAM_EN TSEG_EN
0
X
X
1
0
0
1
0
1
1
1
0
1
1
1
Compatible
(C) Range
Disable
Enable
Enable
Disabled
Disabled
High (H)
Range
Disable
Disable
Disable
Enable
Enable
TSEG (T)
Range
Disable
Disable
Enable
Disable
Enable
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS software
can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range
access to only SMM mode accesses. The D_CLS bit causes SMM (both CSEG and TSEG)
data accesses to be forwarded to the DMI Interface or PCI Express. The SMM software
can use this bit to write to video memory while running SMM code out of DRAM.
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