AC82G41SLGQ3 Datasheet, PDF (339/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.22 MUA— Message Signaled Interrupt Upper Address
(Optional)
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
94-97h
00000000h
R/W
32 bits
Bit
31:0
Access
R/W
Default
Value
00000000h
RST/PWR
Description
Core
Upper Address (UADDR): Upper 32 bits of the system
specified message address. This register is optional and
only implemented if MC.C64=1.
10.2.23 MD— Message Signaled Interrupt Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
98-99h
0000h
R/W
16 bits
Bit
15:0
Access
R/W
Default
Value
0000h
RST/PWR
Description
Core
Data (Data): This 16-bit field is programmed by system
software if MSI is enabled. Its content is driven onto the
FSB during the data phase of the MSI memory write
transaction.
10.2.24 HIDM—HECI Interrupt Delivery Mode
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/3/1/PCI
A0h
00h
R/W
8 bits
00h
This register is used to select interrupt delivery mechanism for HECI to Host processor
interrupts.
Bit
Access
Default
Value
RST/PWR
Description
7:2
RO
0h
Reserved
HECI Interrupt Delivery Mode (HIDM): These bits
control what type of interrupt the HECI will send when ARC
writes to set the M_IG bit in AUX space. They are
1:0
R/W
00b
Core
interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
Datasheet
339