AC82G41SLGQ3 Datasheet, PDF (171/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.3.4
EPLE2D—EP Link Entry 2 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
60-63h
02000002h
RO, R/WO
32 bits
This register provides the first part of a Link Entry, which declares an internal link to
another Root Complex Element.
Bit
Access
31:24
RO
23:16
R/WO
15:2
RO
1
RO
0
R/WO
Default
Value
02h
00h
0000h
1b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Target Port Number (TPN): This field specifies the port
number associated with the element targeted by this link
entry (PEG0). The target port number is with respect to the
component that contains this element as specified by the
target component ID.
Target Component ID (TCID): This field identifies the
physical or logical component that is targeted by this link
entry. A value of 0 is reserved. Component IDs start at 1.
This value is a mirror of the value in the Component ID
field of all elements in this component.
Reserved
Link Type (LTYP): This bit indicates that the link points to
configuration space of the integrated device which controls
the x16 root port for PEG0.
The link address specifies the configuration address
(segment, bus, device, function) of the target root port.
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Datasheet
171