AC82G41SLGQ3 Datasheet, PDF (381/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.8.7
IDEPBMDTPR2—IDE Primary Bus Master Descriptor Table
Pointer Register Byte 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
6h
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Byte 2 (of four bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the primary channel. This register is
programmed by the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 2 (DTPB2):
10.8.8
IDEPBMDTPR3—IDE Primary Bus Master Descriptor Table
Pointer Register Byte 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
7h
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Byte 3 (of four bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the primary channel. This register is
programmed by the Host
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 3 (DTPB3):
Datasheet
381