AC82G41SLGQ3 Datasheet, PDF (38/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Signal Description
Signal Name
FSB_TRDYB
FSB_RSB_[2:0]
FSB_RCOMP
FSB_SCOMP
FSB_SCOMPB
FSB_SWING
FSB_DVREF
FSB_ACCVREF
Type
O
GTL+
O
GTL+
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
Description
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data transfer phase.
Response Signals: Indicates type of response according to
the table at left:
Encoding Response Type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by (G)MCH)
100
Hard Failure (not driven by (G)MCH)
101
No data response
110
Implicit Writeback
111
Normal data response
Host RCOMP: Used to calibrate the Host GTL+ I/O buffers.
This signal is powered by the Host Interface termination rail
(V_TT). Connects to FSB_XRCOMP1IN in the package.
Slew Rate Compensation: Compensation for the Host
Interface for rising edges.
Slew Rate Compensation: Compensation for the Host
Interface for falling edges.
Host Voltage Swing: These signals provide reference
voltages used by the FSB RCOMP circuits. FSB_XSWING is
used for the signals handled by FSB_XRCOMP.
Host Reference Voltage: Reference voltage input for the
Data signals of the Host GTL interface.
Host Reference Voltage: Reference voltage input for the
Address signals of the Host GTL interface.
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Datasheet