AC82G41SLGQ3 Datasheet, PDF (399/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10 KT IO/ Memory Mapped Device Registers
Table 25.
KT IO/ Memory Mapped Device Register Address Map
Address
Offset
0h
0h
0h
Register
Symbol
KTRxBR
KTTHR
KTDLLR
Register Name
KT Receive Buffer Register
KT Transmit Holding Register
KT Divisor Latch LSB Register
1h
KTIER KT Interrupt Enable register
1h
KTDLMR KT Divisor Latch MSB Register
2h
KTIIR KT Interrupt Identification register
2h
KTFCR KT FIFO Control register
3h
KTLCR KT Line Control register
4h
KTMCR KT Modem Control register
5h
KTLSR KT Line Status register
6h
KTMSR KT Modem Status register
7h
KTSCR KT Scratch register
Default
Value
00h
00h
00h
00h
00h
01h
00h
03h
00h
00h
00h
00h
Access
RO/V
WO
R/W/V
R/W/V,
RO/V
R/W/V
RO
WO
R/W
RO, R/W
RO, RO/CR
RO, RO/CR
R/W
10.10.1 KTRxBR—KT Receive Buffer Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
0h
00h
RO/V
8 bits
Reset: Host System Reset or D3->D0 transition.
This implements the KT Receiver Data register. Host access to this address, depends on
the state of the DLAB bit {KTLCR[7]). It must be "0" to access the KTRxBR.
RxBR:
Host reads this register when FW provides it the receive data in non-FIFO mode. In
FIFO mode, host reads to this register translate into a read from ME memory (RBR
FIFO).
Bit
Access
Default
Value
RST/PWR
Description
Receiver Buffer Register (RBR): Implements the Data
7:0
RO/V
00h
Core
register of the Serial Interface. If the Host does a read, it
reads from the Receive Data Buffer.
Datasheet
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