AC82G41SLGQ3 Datasheet, PDF (602/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Testability
16.2 XOR Test Mode Initialization
Figure 24.
An XOR-tree is a chain of XOR gates each with one input pin connected to it, which
allows for pad to ball to trace connection testing.
The XOR testing methodology is to boot the part using straps to enter XOR mode (A
description of the boot process follows). Once in XOR mode, all of the pins of an XOR
chain are driven to logic 1. This action will force the output of that XOR chain to either
a 1 if the number of the pins making up the chain is even or a 0 if the number of the
pins making up the chain is odd.
Once a valid output is detected on the XOR chain output, a walking 0 pattern is moved
from one end of the chain to the other. Every time the walking 0 is applied to a pin on
the chain, the output will toggle. If the output does not toggle, there is a disconnect
somewhere between die, package, and board and the system can be considered a
failure.
XOR Test Mode Initialization Cycles
CL_PWROK
PWROK
CL_RST#
RSTIN#
STRAP PINS
HCLKP/GCLKP
HCLKN/GCLKN
XOR inputs
XOR output
X
Figure 24 shows the wave forms to be able to boot the (G)MCH into XOR mode. The
straps that need to be controlled during this boot process are BSEL[2:0],
SDVO_CTRLDATA, EXP_EN, EXP_SLR, and XORTEST.
All strap values must be driven before PWROK asserts. BSEL0 must be a 1. BSEL[2:1]
need to be defined values, but logic value in any order will work. XORTEST must be
driven to 0.
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Datasheet