AC82G41SLGQ3 Datasheet, PDF (332/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.6
CLS— Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
Ch
00h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Cache Line Size (CLS): Not implemented, hardwired to
0.
10.2.7
MLT— Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
Dh
00h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Master Latency Timer (MLT): Not implemented,
hardwired to 0.
10.2.8
HTYPE— Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
Eh
80h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7
RO
1b
Core
Multi-Function Device (MFD): This bit indicates the
HECI host controller is part of a multi-function device.
6:0
RO
0000000b
Core
Header Layout (HL): This field indicates that the HECI
host controller uses a target device layout.
332
Datasheet