AC82G41SLGQ3 Datasheet, PDF (329/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.1
ID— Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
0-3h
2E058086h
RO
32 bits
Bit
31:16
15:0
Access
RO
RO
Default
Value
2E05h
8086h
RST/PWR
Description
Core
Core
Device ID (DID): Indicates what device number assigned
by Intel.
Vendor ID (VID): 16-bit field which indicates Intel is the
vendor, assigned by the PCI SIG.
10.2.2
CMD— Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
4-5h
0000h
RO, R/W
16 bits
Bit
15:11
10
Access
RO
R/W
9
RO
8
RO
7
RO
6
RO
5
RO
4
RO
3
RO
Default
Value
00000b
0b
0b
0b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
Interrupt Disable (ID): Disables this device from
generating PCI line based interrupts. This bit does not have
any effect on MSI operation.
Fast Back-to-Back Enable (FBE): Not implemented,
hardwired to 0.
SERR# Enable (SEE): Not implemented, hardwired to 0.
Wait Cycle Enable (WCC): Not implemented, hardwired
to 0.
Parity Error Response Enable (PEE): Not implemented,
hardwired to 0.
VGA Palette Snooping Enable (VGA): Not implemented,
hardwired to 0
Memory Write and Invalidate Enable (MWIE): Not
implemented, hardwired to 0.
Special Cycle Enable (SCE): Not implemented,
hardwired to 0.
Datasheet
329