AC82G41SLGQ3 Datasheet, PDF (285/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.14
SID2—Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
2E-2Fh
0000h
R/WO
16 bits
Bit
15:0
Access
R/WO
Default
Value
0000h
RST/PWR
Description
Core
Subsystem Identification (SUBID): This value is used
to identify a particular subsystem. This field should be
programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This register can only be
cleared by a Reset.
9.1.15
ROMADR—Video BIOS ROM Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
30-33h
00000000h
RO
32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
Bit
31:18
17:11
10:1
0
Access
RO
RO
RO
RO
Default
Value
0000h
00h
000h
0b
RST/PWR
Description
Core
Core
Core
Core
ROM Base Address (RBA): Hardwired to 0s.
Address Mask (ADMSK): Hardwired to 0s to indicate
256 KB address range.
Reserved: Hardwired to 0s.
ROM BIOS Enable (RBE):
0 = ROM not accessible.
9.1.16
CAPPOINT—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
34h
90h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
Capabilities Pointer Value (CPV): This field contains an
offset into the function's PCI Configuration Space for the
first item in the New Capabilities Linked List, the MSI
90h
Core
Capabilities ID registers at address 90h, or the Power
Management capability at D0h.
This value is determined by the configuration in CAPL[0].
Datasheet
285