AC82G41SLGQ3 Datasheet, PDF (4/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
PCI Memory Address Range (TOLUD – 4 GB) .........................................................63
3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) .................................65
3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ............................................................65
3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................................65
3.3.4 High BIOS Area ......................................................................................65
Main Memory Address Space (4 GB to TOUUD) ......................................................66
3.4.1 Memory Re-claim Background ..................................................................67
3.4.2 Memory Reclaiming.................................................................................67
PCI Express* Configuration Address Space ............................................................67
PCI Express* Address Space ...............................................................................68
Graphics Memory Address Ranges (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only) ......................................................................................................69
System Management Mode (SMM) .......................................................................69
3.8.1 SMM Space Definition ..............................................................................69
3.8.2 SMM Space Restrictions ...........................................................................70
3.8.3 SMM Space Combinations ........................................................................70
3.8.4 SMM Control Combinations.......................................................................70
3.8.5 SMM Space Decode and Transaction Handling.............................................71
3.8.6 Processor WB Transaction to an Enabled SMM Address Space .......................71
3.8.7 SMM Access Through GTT TLB (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43,
82G41 GMCH Only).................................................................................71
Memory Shadowing............................................................................................72
I/O Address Space .............................................................................................72
3.10.1 PCI Express* I/O Address Mapping............................................................73
(G)MCH Decode Rules and Cross-Bridge Address Mapping .......................................73
3.11.1 Legacy VGA and I/O Range Decode Rules ..................................................73
4 Register Description ................................................................................................75
4.1 Register Terminology .........................................................................................76
4.2 Configuration Process and Registers .....................................................................77
4.2.1 Platform Configuration Structure...............................................................77
4.3 Configuration Mechanisms ..................................................................................78
4.3.1 Standard PCI Configuration Mechanism......................................................78
4.3.2 PCI Express* Enhanced Configuration Mechanism .......................................78
4.4 Routing Configuration Accesses ...........................................................................80
4.4.1 Internal Device Configuration Accesses ......................................................81
4.4.2 Bridge Related Configuration Accesses.......................................................81
4.4.2.1 PCI Express* Configuration Accesses ...........................................81
4.4.2.2 DMI Configuration Accesses ........................................................82
4.5 I/O Mapped Registers.........................................................................................82
4.5.1 CONFIG_ADDRESS—Configuration Address Register ....................................82
4.5.2 CONFIG_DATA—Configuration Data Register ..............................................84
5 DRAM Controller Registers (D0:F0) ..........................................................................85
5.1 DRAM Controller Registers (D0:F0) ......................................................................85
5.1.1 VID—Vendor Identification .......................................................................87
5.1.2 DID—Device Identification .......................................................................87
5.1.3 PCICMD—PCI Command ..........................................................................88
5.1.4 PCISTS—PCI Status ................................................................................89
5.1.5 RID—Revision Identification .....................................................................90
5.1.6 CC—Class Code ......................................................................................91
5.1.7 MLT—Master Latency Timer......................................................................91
5.1.8 HDR—Header Type .................................................................................92
5.1.9 SVID—Subsystem Vendor Identification .....................................................92
5.1.10 SID—Subsystem Identification..................................................................92
5.1.11 CAPPTR—Capabilities Pointer ....................................................................93
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Datasheet