AC82G41SLGQ3 Datasheet, PDF (438/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
24
23
22:0
Access
RO
RO
RO
Default
Value
0b
0b
000000h
RST/PWR
Description
Core
Core
Core
Interrupt Remapping Table Pointer Status (IRTPS):
This field indicates the status of the interrupt remapping
table pointer in hardware.
This field is cleared by hardware when software sets the
SIRTP field in the Global Command register. This field is
Set by hardware when hardware completes the set
interrupt remap table pointer operation using the value
provided in the Interrupt Remapping Table Address
register.
Compatibility Format Interrupt Status (CFIS): This
field indicates the status of Compatibility format interrupts
on Intel 64 implementations supporting interrupt-
remapping. The value reported in this field is applicable
only when interrupt-remapping is enabled and Legacy
interrupt mode is active.
0 = Compatibility format interrupts are blocked.
1 = Compatibility format interrupts are processed as pass-
through (bypassing interrupt remapping).
Reserved
12.1.6
RTADDR_REG—Root-Entry Table Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/VC0PREMAP
20-27h
0000000000000000h
R/W, RO
64 bits
This register provides the base address of root-entry table.
Bit
63:12
11:0
Access
R/W
RO
Default
Value
000000000
0000h
000h
RST/PWR
Description
Core
Core
Root table address (RTA): This register points to base of
page aligned, 4 KB-sized root-entry table in system
memory. Hardware may ignore and not implement bits
63:HAW, where HAW is the host address width.
Software specifies the base address of the root-entry table
through this register, and programs it in hardware through
the SRTP field in the Global Command register.
Reads of this register returns value that was last
programmed to it.
Reserved
438
Datasheet