AC82G41SLGQ3 Datasheet, PDF (130/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.6
Table 12.
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
208-209h
0000h
R/W/L
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
Ch0 Rank2, 3:
Ch1 Rank0, 1:
Ch1 Rank2, 3:
208h-209h
20Ah-20Bh
608h - 609h
60Ah - 60Bh
DRA[6:0] = "00" means cfg0, DRA[6:0] ="01" means cfg1.... DRA[6:0] = "09" means
cfg9 and so on.
DRA[7] indicates whether it's an 8 bank config or not. DRA[7] = 0 means 4 bank,
DRA[7] = 1 means 8 bank.
DRAM Rank Attribute Register Programming
Cfg
Tech DDRx Depth Width Row Col Bank Size
Size
0
256Mb
2
32M
8
1
256Mb
2
16M
16
2
512Mb
2
64M
8
3
512Mb
2
32M
16
4
512Mb
3
64M
8
5
512Mb
3
32M
16
6
1 Gb
2,3
128M
8
7
1 Gb
2,3
64M
16
8
2 Gb
2,3
256M
8
13
10
13
9
14
10
13
10
13
10
12
10
14
10
13
10
15
10
2
256 MB 8K
2
128 MB 4K
2
512 MB 8k
2
256 MB 8k
3
512 MB 8k
3
256 MB 8k
3
1 GB
8k
3
512 MB 8k
3
2 GB
8k
9
2 Gb
2,3
128M
16
14
10
3
1 GB
8k
Bit
15:8
7:0
Access
R/W/L
R/W/L
Default
Value
00h
00h
RST/PWR
Description
Core
Core
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This
register defines DRAM pagesize/number-of-banks for
rank1 for given channel. See Table 12.
This register is locked by ME stolen Memory lock.
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This
register defines DRAM page size/number-of-banks for
rank0 for given channel. See Table 12.
This register is locked by ME stolen Memory lock.
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Datasheet