AC82G41SLGQ3 Datasheet, PDF (547/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13.8.2
ME Power States
ME power states and Host/ME state combinations are described in the following tables.
MState
Moff
M1
M0
Description
ME off
ME is running at slow speed, using its own memory controller which can access
ch0 memory.
ME is running at full speed using the host memory controller to access UMA.
Table 37.
13.8.3
Host/ME State Combinations
Given Host State
S0
S3, S4, S5
M0, Moff
M1, Moff
Allowable ME states
Host/ME State Transitions
Scenario 1: S5/Moff (G3) to S0/M0
• BIOS detects memory and initializes system memory controller
• ME waits for BIOS message before moving from Moff to M0
• BIOS sends ME information about the DIMMs, which ME stores into flash
Scenario 2: S(x)/M1 to S0/M0
• BIOS asks already running ME to recover DIMM timing parameters from flash
• BIOS initializes host memory controller
• BIOS notifies ME that high performance memory is available and it transitions from
M1 to M0
Scenario 3: S(x)/Moff to Sx/M1
• After initial boot (S5/Moff to S0/M0), memory configuration is saved in flash
• Wake event triggers switch to Sx/M1
• Memory configuration loaded and BSEL information supplied to clock chip
• Transition takes place
Datasheet
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