AC82G41SLGQ3 Datasheet, PDF (164/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.46
THERM1—Hardware Throttle Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CE4h
00h
RO, R/W/L, R/W/L/K
8 bits
All bits in this register are reset to their defaults by PLTRST#.
Bit
Access
Default
Value
RST/PWR
Description
7
R/W/L
0b
6
R/W/L
0b
5
RO
0b
4
R/W/L
0b
3
R/W/L
0b
2:1
RO
00b
0
R/W/L/K
0b
Core
Core
Core
Core
Core
Core
Core
Internal Thermal Hardware Throttling Enable
(ITHTE): This bit is a master enable for internal thermal
sensor-based hardware throttling.
0 = Hardware actions via the internal thermal sensor are
disabled.
1 = Hardware actions via the internal thermal sensor are
enabled.
Internal Thermal Hardware Throttling Type (ITHTT):
This policy bit determines what type of hardware throttling
will be enacted by the internal thermal sensor when
enabled by ITHTE:
0 = (G)MCH throttling
1 = DRAM throttling
Reserved
Throttling Temperature Range Selection (TTRS): This
bit determines what temperature ranges will enable
throttling. Lockable by bit 0 of this register. See also the
throttling registers in MCHBAR configuration space C0GTC
and C1GTC [(G)MCH Thermal Sensor Trip Enable] and
PEFC [Thermal Sensor Trip Enable] which are used to
enable or disable throttling.
0 = Catastrophic only. The Catastrophic thermal
temperature range will enable main memory thermal
throttling.
1 = Hot and Catastrophic.
Halt on Catastrophic (HOC):
0 = Continue to toggle clocks when the catastrophic sensor
trips.
1 = All clocks are disabled when the catastrophic sensor
trips. A system reset is required to bring the system
out of a halt from the thermal sensor.
Reserved
Hardware Throttling Lock Bit (HTL): This bit locks bits
7:0 of this register.
0 = The register bits are unlocked.
1 = The register bits are locked. It may only be set to a 0
by a hardware reset.
Writing a 0 to this bit has no effect.
164
Datasheet