AC82G41SLGQ3 Datasheet, PDF (268/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.49
PVCCAP2—Port VC Capability Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
108–10Bh
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Bit
31:24
23:0
Access
RO
RO
Default
Value
00h
0000h
RST/
PWR
Core
Core
Description
VC Arbitration Table Offset (VCATO): This field indicates the
location of the VC Arbitration Table. This field contains the zero-based
offset of the table in DQWORDS (16 bytes) from the base address of
the Virtual Channel Capability Structure. A value of 0 indicates that
the table is not present (due to fixed VC priority).
Reserved
8.50
PVCCTL—Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
10C–10Dh
0000h
RO, RW
16 bits
Bit
15:4
3:1
0
Access
RO
RW
RO
Default
Value
000h
000b
0b
RST/
PWR
Core
Core
Core
Description
Reserved
VC Arbitration Select (VCAS): This field will be programmed by
software to the only possible value as indicated in the VC Arbitration
Capability field. Since there is no other VC supported than the default,
this field is reserved.
Reserved
268
Datasheet