AC82G41SLGQ3 Datasheet, PDF (401/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.4 KTIER—KT Interrupt Enable Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
1h
00h
R/W/V, RO/V
8 bits
Reset: Host System Reset or D3 -> D0 transition
This implements the KT Interrupt Enable register. Host access to this address, depends
on the state of the DLAB bit {KTLCR[7]). It must be "0" to access this register. The bits
enable specific events to interrupt the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:4
RO/V
0h
3
R/W/V
0b
Core
Core
Reserved
MSR (IER2): When set, this bit enables bits in the Modem
Status register to cause an interrupt to the host.
2
R/W/V
0b
1
R/W/V
0b
0
R/W/V
0b
Core
Core
Core
LSR (IER1): When set, this bit enables bits in the
Receiver Line Status Register to cause an Interrupt to the
Host.
THR (IER1): When set, this bit enables an interrupt to be
sent to the Host when the transmit Holding register is
empty.
DR (IER0): When set, the Received Data Ready (or
Receive FIFO Timeout) interrupts are enabled to be sent to
Host.
10.10.5 KTDLMR—KT Divisor Latch MSB Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
1h
00h
R/W/V
8 bits
Reset: Host System Reset or D3->D0 transition.
Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this
bit is 0, Host accesses the KTIER.
This is the standard Serial interface's Divisor Latch register's MSB. This register is only
for SW compatibility and does not affect performance of the hardware.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
Divisor Latch MSB (DLM): Implements the Divisor Latch
MSB register of the Serial Interface.
Datasheet
401