AC82G41SLGQ3 Datasheet, PDF (360/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.24 MA—Message Signaled Interrupt Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
D4-D7h
00000000h
R/W, RO
32 bits
Reset: Host system Reset or D3->D0 transition
This register specifies the DWORD aligned address programmed by system software for
sending MSI.
Bit
31:2
1:0
Access
R/W
RO
Default
Value
00000000h
00b
RST/PWR
Description
Core
Core
Address (ADDR): This field contains the Lower 32 bits of
the system specified message address, always DWord
aligned
Reserved
10.5.25 MAU—Message Signaled Interrupt Message Upper Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
D8-DBh
00000000h
RO, R/W
32 bits
Reset: Host system Reset or D3->D0 transition
Upper 32 bits of the message address for the 64bit address capable device.
Bit
31:4
3:0
Access
RO
R/W
Default
Value
0000000h
0000b
RST/PWR
Description
Core
Core
Reserved
Address (ADDR): This field contains the Upper 4 bits of
the system specified message address.
10.5.26 MD—Message Signaled Interrupt Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
DC-DDh
0000h
R/W
16 bits
Reset: Host system Reset or D3->D0 transition
This 16-bit field is programmed by system software if MSI is enabled.
Bit
15:0
Access
R/W
Default
Value
0000h
RST/PWR
Description
Core
Data (DATA): This content is driven onto the lower word
of the data bus of the MSI memory write transaction.
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