AC82G41SLGQ3 Datasheet, PDF (603/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Testability
16.2.1
If sDVO is present in the design, SDVO_CTRLDATA must be pulled to logic 1. Depending
on if Static Lane Reversal is used and if the sDVO/PCIe Coexistence is selected,
EXP_SLR and EXP_EN must be pulled in a valid manner.
XOR Chain Definition
For the (G)MCH XOR chain definitions, contact your Intel field representative.
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Datasheet
603