AC82G41SLGQ3 Datasheet, PDF (143/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.22
C1CYCTRKACT—Channel 1 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
652-655h
00000000h
R/W, RO
32 bits
Bit
31:30
29
28
27:22
21
20:17
16:13
12:9
8:0
Access
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Value
RST/PWR
Description
0h
0b
0b
000000b
0b
0000b
0000b
0h
000000000b
Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
FAW Windowcnt Bug Fix Disable
(C1sd_cr_cyctrk_faw_windowcnt_fix_disable): This
field disables the CYCTRK FAW windowcnt bug fix.
1 = Disable CYCTRK FAW windowcnt bug fix
0 = Enable CYCTRK FAW windowcnt bug fix
FAW Phase Bug Fix Disable
(C1sd_cr_cyctrk_faw_phase_fix_disable): This field
disables the CYCTRK FAW phase indicator bug fix.
1 = Disable CYCTRK FAW phase indicator bug fix
0 = Enable CYCTRK FAW phase indicator bug fix
ACT Window Count (C1sd_cr_act_windowcnt): This
field indicates the window duration (in DRAM clocks)
during which the controller counts the # of activate
commands which are launched to a particular rank. If the
number of activate commands launched within this
window is greater than 4, then a check is implemented to
block launch of further activates to this rank for the rest of
the duration of this window.
Max ACT Check (C1sd_cr_maxact_dischk): This field
enables the check which ensures that there are no more
than four activates to a particular rank in a given window.
ACT to ACT Delayed (C1sd_cr_act_act[): This field
indicates the minimum allowed spacing (in DRAM clocks)
between two ACT commands to the same rank. This field
corresponds to tRRD in the DDR Specification.
PRE to ACT Delayed (C1sd_cr_pre_act): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the PRE and ACT commands to the same rank-
bank:12:9R/W0000bPRE-ALL to ACT Delayed
(C1sd_cr_preall_act):. This configuration register
indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and ACT commands to the same
rank. This field corresponds to tRP in the DDR
Specification.
ALLPRE to ACT Delay (C1sd_cr_preall_act): From the
launch of a prechargeall command wait for this number of
memory clocks before launching a activate command. This
field corresponds to tPALL_RP in the DDR specification.
REF to ACT Delayed (C1sd_cr_rfsh_act): This field
indicates the minimum allowed spacing (in DRAM clocks)
between REF and ACT commands to the same rank. This
field corresponds to tRFC in the DDR Specification.
Datasheet
143