AC82G41SLGQ3 Datasheet, PDF (37/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Signal Description
Signal Name
Type
Description
FSB_AB_[35:3]
FSB_ADSTBB_[1:0]
FSB_DB_[63:0]
FSB_DSTBPB_[3:0]
FSB_DSTBNB_[3:0]
FSB_HITB
FSB_HITMB
FSB_LOCKB
FSB_REQB_[4:0]
I/O
GTL+ 2x
Host Address Bus: FSB_AB_[35:3] connect to the processor
address bus. During processor cycles the FSB_AB_[35:3] are
inputs. The (G)MCH drives FSB_AB_[35:3] during snoop cycles
on behalf of DMI and PCI Express initiators. FSB_AB_[35:3]
are transferred at 2x rate. Note that the address is inverted on
the processor bus. The values are driven by the (G)MCH
between PWROK assertion and FSB_CPURSTINB deassertion to
allow processor configuration.
I/O
GTL+ 2x
Host Address Strobe: The source synchronous strobes used
to transfer FSB_AB_[31:3] and FSB_REQB_[4:0] at the 2x
transfer rate.
Strobe
Address Bits
FSB_ADSTBB_0
FSB_AB_[16:3], FSB_REQB_[4:0]
FSB_ADSTBB_1
FSB_AB_[31:17]
I/O
GTL+ 4x
Host Data: These signals are connected to the processor data
bus. Data on FSB_DB_[63:0] is transferred at a 4x rate. Note
that the data signals may be inverted on the processor bus,
depending on the FSB_DINVB_[3:0] signals.
I/O
GTL+ 4x
Differential Host Data Strobes: The differential source
synchronous strobes used to transfer FSB_DB_[63:0] and
FSB_DINVB_[3:0] at the 4x transfer rate.
Named this way because they are not level sensitive. Data is
captured on the falling edge of both strobes. Hence, they are
pseudo-differential, and not true differential.
Strobe
Data Bits
FSB_DSTB[P,N]B_3 FSB_DB_[63:48], HDINVB_3
FSB_DSTB[P,N]B_2 FSB_DB_[47:32], HDINVB_2
FSB_DSTB[P,N]B_1 FSB_DB_[31:16], HDINVB_1
FSB_DSTB[P,N]B_0 FSB_DB_[15:0], HDINVB_0
I/O
GTL+
Hit: Indicates that a caching agent holds an unmodified
version of the requested line. Also, driven in conjunction with
FSB_HITMB by the target to extend the snoop window.
I/O
GTL+
Hit Modified: Indicates that a caching agent holds a modified
version of the requested line and that this agent assumes
responsibility for providing the line. Also, driven in conjunction
with FSB_HITB to extend the snoop window.
I
GTL+
Host Lock: All processor bus cycles sampled with the
assertion of FSB_LOCKB and FSB_ADSB, until the negation of
FSB_LOCKB must be atomic, i.e. no DMI or PCI Express access
to DRAM are allowed when FSB_LOCKB is asserted by the
processor.
I/O
GTL+
2x
Host Request Command: Defines the attributes of the
request. FSB_REQB_[4:0] are transferred at 2x rate. Asserted
by the requesting agent during both halves of Request Phase.
In the first half the signals define the transaction type to a level
of detail that is sufficient to begin a snoop request. In the
second half the signals carry additional information to define
the complete transaction type.
The transactions supported by the (G)MCH Host Bridge are
defined in the Host Interface section of this document.
Datasheet
37