AC82G41SLGQ3 Datasheet, PDF (300/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.2.4
PCISTS2—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
6-7h
0090h
RO
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that
has been set by the IGD.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
00b
0b
1b
0b
0b
1b
0b
000b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Detected Parity Error (DPE): Since the IGD does not
detect parity, this bit is always hardwired to 0.
Signaled System Error (SSE): The IGD never asserts
SERR#, therefore this bit is hardwired to 0.
Received Master Abort Status (RMAS): The IGD never
gets a Master Abort, therefore this bit is hardwired to 0.
Received Target Abort Status (RTAS): The IGD never
gets a Target Abort, therefore this bit is hardwired to 0.
Signaled Target Abort Status (STAS): Hardwired to 0.
The IGD does not use target abort semantics.
DEVSEL Timing (DEVT): N/A. These bits are hardwired
to "00".
Master Data Parity Error Detected (DPD): Since Parity
Error Response is hardwired to disabled (and the IGD does
not do any parity detection), this bit is hardwired to 0.
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD
accepts fast back-to-back when the transactions are not to
the same agent.
User Defined Format (UDF): Hardwired to 0.
66 MHz PCI Capable (66C): N/A - Hardwired to 0.
Capability List (CLIST): This bit is set to 1 to indicate
that the register at 34h provides an offset into the
function's PCI Configuration Space containing a pointer to
the location of the first item in the list.
Interrupt Status (INTSTS): Hardwired to 0.
Reserved
300
Datasheet