AC82G41SLGQ3 Datasheet, PDF (203/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
18
RO
17:15
R/WO
14:12
11:10
9:4
RO
R/WO
R/WO
3:0
R/WO
Default
Value
0b
010b
100b
11b
10h
2h
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Clock Power Management (CPM): A value of 1b in this
bit indicates that the component tolerates the removal of
any reference clock(s) when the link is in the L1 and L2/3
Ready link states. A value of 0b indicates the component
does not have this capability and that reference clock(s)
must not be removed in these link states.
This capability is applicable only in form factors that
support "clock request" (CLKREQ#) capability.
For a multi-function device, each function indicates its
capability independently. Power Management configuration
software must only permit reference clock removal if all
functions of the multifunction device indicate a 1b in this
bit.
L1 Exit Latency (L1ELAT): This field indicates the length
of time this Port requires to complete the transition from
L1 to L0. The value 010 b indicates the range of 2 us to
less than 4 us.
BIOS Requirement: If this field is required to be any
value other than the default, BIOS must initialize it
accordingly.
Both bytes of this register that contain a portion of this
field must be written simultaneously in order to prevent an
intermediate (and undesired) value from ever existing.
Reserved
Active State Link PM Support (ASLPMS): The (G)MCH
supports ASPM L1.
Max Link Width (MLW): This field indicates the
maximum number of lanes supported for this link.
Max Link Speed (MLS): Supported Link Speed – This
field indicates the supported Link speed(s) of the
associated Port. Defined encodings are:
0001b = 2.5 GT/s Link speed supported
0010b = 5.0 GT/s and 2.5GT/s Link speeds supported
All other encodings are reserved.
Datasheet
203