AC82G41SLGQ3 Datasheet, PDF (108/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.24
Note:
PAM6—Programmable Attribute Map 6
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
96h
00h
RO, R/W/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h–0EFFFFh.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
Access
Default
Value
RST/PWR
Description
7:6
RO
00b
5:4
R/W/L
00b
3:2
RO
00b
1:0
R/W/L
00b
Core
Core
Core
Core
Reserved
0EC000h-0EFFFFh Attribute (HIENABLE): This field
controls the steering of read and write cycles that address
the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
Reserved
0E8000h-0EBFFFh Attribute (LOENABLE): This field
controls the steering of read and write cycles that address
the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
108
Datasheet