AC82G41SLGQ3 Datasheet, PDF (183/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.13
IOLIMIT1—I/O Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1Dh
00h
R/W, RO
8 bits
This register controls the processor-to-PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode, address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
Bit
Access
Default
Value
RST/PWR
Description
I/O Address Limit (IOLIMIT): This field corresponds to
7:4
R/W
0h
Core
A[15:12] of the I/O address limit of device 1. Devices
between this upper limit and IOBASE1 will be passed to the
PCI Express hierarchy associated with this device.
3:0
RO
0h
Core
Reserved
6.1.14
SSTS1—Secondary Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1E-1Fh
0000h
R/WC, RO
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express-G side) of the "virtual" PCI-PCI bridge
in the (G)MCH.
Bit
Access
Default
Value
RST/PWR
Description
15
R/WC
0b
14
R/WC
0b
13
R/WC
0b
Core
Core
Core
Detected Parity Error (DPE): This bit is set by the
Secondary Side for a Type 1 Configuration Space header
device whenever it receives a Poisoned TLP, regardless of
the state of the Parity Error Response Enable bit in the
Bridge Control Register.
Received System Error (RSE): This bit is set when the
Secondary Side for a Type 1 configuration space header
device receives an ERR_FATAL or ERR_NONFATAL.
Received Master Abort (RMA): This bit is set when the
Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device
itself) receives a Completion with Unsupported Request
Completion Status.
Datasheet
183