AC82G41SLGQ3 Datasheet, PDF (198/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.31
MA—Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
94-97h
00000000h
R/W, RO
32 bits
Bit
31:2
1:0
Access
R/W
RO
Default
Value
00000000h
00b
RST/PWR
Description
Core
Core
Message Address (MA): This field is used by system
software to assign an MSI address to the device. The
device handles an MSI by writing the padded contents of
the MD register to this address.
Force DWord Align (FDWA): Hardwired to 0 so that
addresses assigned by system software are always aligned
on a dword address boundary.
6.1.32
MD—Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
98-99h
0000h
R/W
16 bits
Bit
15:0
Access
R/W
Default
Value
0000h
RST/PWR
Description
Core
Message Data (MD): This field is the base message data
pattern assigned by system software and used to handle
an MSI from the device.
When the device must generate an interrupt request, it
writes a 32-bit value to the memory address specified in
the MA register. The upper 16 bits are always set to 0. The
lower 16 bits are supplied by this register.
6.1.33
PEG_CAPL—PCI Express-G Capability List
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A0-A1h
0010h
RO
16 bits
This register enumerates the PCI Express capability structure.
Bit
15:8
7:0
Access
RO
RO
Default
Value
00h
10h
RST/PWR
Description
Core
Core
Pointer to Next Capability (PNC): This value terminates
the capabilities list. The Virtual Channel capability and any
other PCI Express specific capabilities that are reported via
this mechanism are in a separate capabilities list located
entirely within PCI Express Extended Configuration Space.
Capability ID (CID): This field identifies this linked list
item (capability structure) as being for PCI Express
registers.
198
Datasheet