AC82G41SLGQ3 Datasheet, PDF (229/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8 Host-Secondary PCI Express*
Bridge Registers (D6:F0)
(Intel^® 82P45 MCH Only)
Warning:
Note:
Table 14.
Device 6 contains the controls associated with the PCI Express root port that is the
intended attach point for external devices. In addition, it also functions as the virtual
PCI-to-PCI bridge. Table 14 provides an address map of the D1:F0 registers listed by
address offset in ascending order. This chapter provides a detailed bit description of the
registers.
When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits:
Reserved and Preserved:
• Reserved for future RW implementations; software must preserve value read for
writes to bits.
• Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first disable the link, then program the registers, and then re-
enable the link (which will cause a full-retrain with the new settings).
Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 1
of 3)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
0–1h
2–3h
4–5h
6–7h
8h
9–Bh
Ch
Eh
18h
19h
1Ah
1Ch
VID1
DID1
PCICMD1
PCISTS1
Vendor Identification
Device Identification
PCI Command
PCI Status
RID1
Revision Identification
CC1
CL1
HDR1
PBUSN1
SBUSN1
SUBUSN1
IOBASE1
Class Code
Cache Line Size
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
I/O Base Address
8086h
29E9h
0000h
0010h
See register
description
060400h
00h
01h
00h
00h
00h
F0h
RO
RO
RO, RW
RO, RWC
RO
RO
RW
RO
RO
RW
RW
RO, RW
Datasheet
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