AC82G41SLGQ3 Datasheet, PDF (94/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.13
MCHBAR—(G)MCH Memory Mapped Register Range Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
48-4Fh
0000000000000000h
R/W/L, RO
64 bits
This is the base address for the (G)MCH Memory Mapped Configuration space. There is
no physical memory within this 16 KB window that can be addressed. The 16 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the (G)MCH MMIO Memory Mapped Configuration space is disabled
and must be enabled by writing a 1 to MCHBAREN [Device 0, offset48h, bit 0].
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
63:36
35:14
13:1
0
Access
RO
R/W/L
RO
R/W/L
Default
Value
0000000h
000000h
0000h
0b
RST/PWR
Description
Core
Core
Core
Core
Reserved
(G)MCH Memory Mapped Base Address (MCHBAR):
This field corresponds to bits 35:14 of the base address
(G)MCH Memory Mapped configuration space. BIOS will
program this register resulting in a base address for a
16 KB block of contiguous memory address space. This
register ensures that a naturally aligned 16 KB space is
allocated within the first 64GB of addressable memory
space. System Software uses this base address to program
the (G)MCH Memory Mapped register set.
Reserved
MCHBAR Enable (MCHBAREN):
0 = MCHBAR is disabled and does not claim any memory
1 = MCHBAR memory mapped accesses are claimed and
decoded appropriately
94
Datasheet