AC82G41SLGQ3 Datasheet, PDF (404/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.8 KTLCR—KT Line Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
3h
03h
R/W
8 bits
Reset: Host System Reset or D3->D0 transition.
The line control register specifies the format of the asynchronous data communications
exchange and sets the DLAB bit. Most bits in this register have no affect on hardware
and are only used by the FW.
Bit
Access
Default
Value
RST/PWR
Description
Divisor Latch Address Bit (DLAB): This bit is set when
the Host wants to read/write the Divisor Latch LSB and
7
R/W
0b
Core
MSB Registers. This bit is cleared when the Host wants to
access the Receive Buffer Register or the Transmit Holding
Register or the Interrupt Enable Register.
6
R/W
0b
Core
Break Control (BC): This bit has no affect on hardware.
5:4
R/W
00b
Core
Parity Bit Mode (PBM): This bit has no affect on
hardware.
3
R/W
0b
Core
Parity Enable (PE): This bit has no affect on hardware.
2
R/W
0b
Core
Stop Bit Select (SBS): This bit has no affect on
hardware.
1:0
R/W
11b
Core
Word Select Byte (WSB): This bit has no affect on
hardware.
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