AC82G41SLGQ3 Datasheet, PDF (284/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.12
IOBAR—I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
20-23h
00000001h
RO, R/W
32 bits
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16 bit I/O Address
Space. Bits 2:1 are fixed and return zero, bit 0 is hardwired to a 1 indicating that 8
bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state
D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if IO
Enable is clear or if Device 2 is turned off or if internal graphics is disabled through the
fuse or fuse override mechanisms.
Note that access to this IO BAR is independent of VGA functionality within Device 2.
Also, note that this mechanism is available only through Function 0 of Device 2 and is
not duplicated in Function 1.
If accesses to this IO bar is allowed then the GMCH claims all 8, 16, or 32 bit I/O cycles
from the processor that falls within the 8B claimed.
Bit
31:16
15:3
2:1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
0000h
00b
1b
RST/PWR
Description
Core
FLR, Core
Core
Core
Reserved
IO Base Address (IOBASE): This field is set by the OS,
these bits correspond to address signals 15:3.
Memory Type (MEMTYPE): Hardwired to 0s to indicate
32-bit address.
Memory/IO Space (MIOS): Hardwired to 1 to indicate
I/O space.
9.1.13
SVID2—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
2C-2Dh
0000h
R/WO
16 bits
Bit
15:0
Access
R/WO
Default
Value
0000h
RST/PWR
Description
Core
Subsystem Vendor ID (SUBVID): This value is used to
identify the vendor of the subsystem. This register should
be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This register can only be
cleared by a Reset.
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Datasheet