AC82G41SLGQ3 Datasheet, PDF (10/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

9.2.18 MGGC—Mirror of Device 0 GMCH Graphics Control Register ........................ 306
9.2.19 DEVEN—Device Enable .......................................................................... 308
9.2.20 SSRW—Mirror of Function 0 Software Scratch Read Write........................... 309
9.2.21 BSM—Mirror of Function 0 Base of Stolen Memory..................................... 310
9.2.22 HSRW—Mirror of Device 2 Function 0 Hardware Scratch Read Write ............ 310
9.2.23 GDRST—Mirror of Device 2 Function 0 Graphics Reset ............................... 311
9.2.24 PMCAPID—Mirror of Fun 0 Power Management Capabilities ID..................... 312
9.2.25 PMCAP—Mirror of Fun 0 Power Management Capabilities ............................ 312
9.2.26 PMCS—Power Management Control/Status ............................................... 313
9.2.27 SWSMI—Mirror of Func0 Software SMI .................................................... 313
10 Intel^® Manageability Engine Subsystem Registers ................................................. 315
10.1 HECI Function in ME subsystem Registers ........................................................... 315
10.1.1 ID— Identifiers..................................................................................... 316
10.1.2 CMD— Command.................................................................................. 316
10.1.3 STS— Device Status.............................................................................. 317
10.1.4 RID— Revision ID ................................................................................. 318
10.1.5 CC— Class Code ................................................................................... 318
10.1.6 CLS— Cache Line Size ........................................................................... 319
10.1.7 MLT— Master Latency Timer................................................................... 319
10.1.8 HTYPE— Header Type............................................................................ 319
10.1.9 BIST— Built In Self Test ........................................................................ 320
10.1.10HECI_MBAR— HECI MMIO Base Address .................................................. 320
10.1.11SS— Sub System Identifiers................................................................... 321
10.1.12CAP— Capabilities Pointer ...................................................................... 321
10.1.13INTR— Interrupt Information ................................................................. 322
10.1.14MGNT— Minimum Grant ........................................................................ 322
10.1.15MLAT— Maximum Latency...................................................................... 322
10.1.16HFS— Host Firmware Status................................................................... 323
10.1.17PID— PCI Power Management Capability ID ............................................. 323
10.1.18PC— PCI Power Management Capabilities ................................................. 324
10.1.19PMCS— PCI Power Management Control And Status .................................. 325
10.1.20MID— Message Signaled Interrupt Identifiers ........................................... 326
10.1.21MC— Message Signaled Interrupt Message Control .................................... 326
10.1.22MA— Message Signaled Interrupt Message Address ................................... 326
10.1.23MUA— Message Signaled Interrupt Upper Address (Optional)...................... 327
10.1.24MD— Message Signaled Interrupt Message Data ....................................... 327
10.2 Second HECI Function in ME Subsystem Registers................................................ 328
10.2.1 ID— Identifiers..................................................................................... 329
10.2.2 CMD— Command.................................................................................. 329
10.2.3 STS— Device Status.............................................................................. 330
10.2.4 RID—Revision ID .................................................................................. 331
10.2.5 CC— Class Code ................................................................................... 331
10.2.6 CLS— Cache Line Size ........................................................................... 332
10.2.7 MLT— Master Latency Timer................................................................... 332
10.2.8 HTYPE— Header Type............................................................................ 332
10.2.9 HECI_MBAR— HECI MMIO Base Address .................................................. 333
10.2.10SS— Sub System Identifiers................................................................... 333
10.2.11CAP— Capabilities Pointer ...................................................................... 334
10.2.12INTR— Interrupt Information ................................................................. 334
10.2.13MGNT— Minimum Grant ........................................................................ 334
10.2.14MLAT— Maximum Latency...................................................................... 335
10.2.15HFS— Host Firmware Status................................................................... 335
10.2.16PID— PCI Power Management Capability ID ............................................. 335
10.2.17PC— PCI Power Management Capabilities ................................................. 336
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