AC82G41SLGQ3 Datasheet, PDF (199/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.34
PEG_CAP—PCI Express-G Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A2-A3h
0142h
RO, R/WO
16 bits
This register indicates PCI Express device capabilities.
Bit
15:14
13:9
Access
RO
RO
8
R/WO
7:4
RO
3:0
RO
Default
Value
0b
00h
1b
4h
2h
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
Interrupt Message Number (IMN): Not Applicable or
Implemented. Hardwired to 0.
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is
connected to an integrated component or is disabled.
1 = The PCI Express Link associated with this port is
connected to a slot.
BIOS Requirement: This field must be initialized
appropriately if a slot connection is not implemented.
Device/Port Type (DPT): Hardwired to 4h to indicate
root port of PCI Express Root Complex.
PCI Express Capability Version (PCIECV): Hardwired
to 2h to indicate compliance to the PCI Express Capabilities
Register Expansion ECN.
6.1.35
DCAP—Device Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
A4-A7h
00008000h
RO
32 bits
This register indicates PCI Express device capabilities.
Bit
31:16
Access
RO
15
RO
14:6
RO
5
RO
4:3
RO
2:0
RO
Default
Value
0000h
1b
000h
0b
00b
000b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Reserved: Not Applicable or Implemented. Hardwired to 0.
Role Based Error Reporting (RBER): This bit indicates
that this device implements the functionality defined in the
Error Reporting ECN as required by the PCI Express 1.1
Specification.
Reserved: Not Applicable or Implemented. Hardwired to 0.
Extended Tag Field Supported (ETFS): Hardwired to
indicate support for 5-bit Tags as a Requestor.
Phantom Functions Supported (PFS): Not Applicable
or Implemented. Hardwired to 0.
Max Payload Size (MPS): Hardwired to indicate 128B
max supported payload for Transaction Layer Packets
(TLP).
Datasheet
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