AC82G41SLGQ3 Datasheet, PDF (402/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.6 KTIIR—KT Interrupt Identification Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
2h
01h
RO
8 bits
Reset: See specific Bit descriptions.
The KT IIR register prioritizes the interrupts from the function into 4 levels and records
them in the IIR_STAT field of the register. When Host accesses the IIR, hardware
freezes all interrupts and provides the priority to the Host. Hardware continues to
monitor the interrupts but does not change its current indication until the Host read is
over. Table in the Host Interrupt Generation section shows the contents.
Bit
Access
Default
Value
RST/PWR
Description
7
RO
6
RO
5:4
RO
3:1
RO
0
RO
0b
0b
00b
000b
1b
Core
Core
Core
Core
Core
FIFO Enable (FIEN1): This bit is connected by hardware
to bit 0 in the FCR register.
Reset: Host System Reset or D3->D0 transition.
FIFO Enable (FIEN0): This bit is connected by hardware
to bit 0 in the FCR register.
Reset: Host System Reset or D3->D0 transition.
Reserved
IIR STATUS (IIRSTS): These bits are asserted by the
hardware according to the source of the interrupt and the
priority level.
Reset: ME system Reset.
Interrupt Status (INTSTS):
0 = Pending interrupt to Host
1 = No pending interrupt to Host
Reset: Host system Reset or D3->D0 transition
402
Datasheet