AC82G41SLGQ3 Datasheet, PDF (345/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.4.2
Note:
H_CSR— Host Control Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/MMIO
4-7h
02000000h
RO, R/W, R/WC
32 bits
This register reports status information about the host circular buffer (H_CB) and
allows host software to control interrupt generation.
Reserved bits in this register must be set to 0 whenever this register is written.
Bit
Access
31:24
RO
23:16
RO
15:8
RO
7:5
RO
4
R/W
3
R/W
Default
Value
02h
00h
00h
000b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Host Circular Buffer Depth (H_CBD): This field
indicates the maximum number of 32 bit entries available
in the host circular buffer (H_CB). Host software uses this
field along with the H_CBRP and H_CBWP fields to
calculate the number of valid entries in the H_CB to read or
number of entries available for write. This field is a read
only version of H_CBD_MERWA field which is programmed
by the ME firmware during ME initialization.
Programer's note: This field is implemented with a "1-
hot" scheme. Only one bit will be set to a 1 at a time. Each
bit position represents the value n of a buffer depth of
(2^n). For example, when bit 0 is 1, the buffer depth is 1;
when bit 1 is 1, the buffer depth is 2, etc. The allowed
buffer depth values are 2, 4, 8, 16, 32, 64 and 128.
This field is reset by MERST#.
Host CB Write Pointer (H_CBWP): This field points to
next location in the H_CB for host to write the data.
Software uses this field along with H_CBRP and H_CBD
fields to calculate the number of valid entries in the H_CB
to read or number of entries available for write.
Host CB Read Pointer (H_CBRP): This field points to
next location in the H_CB where a valid data is available for
embedded controller to read. Software uses this field along
with H_CBWR and H_CBD fields to calculate the number of
valid entries in the host CB to read or number of entries
available for write.
Reserved
Host Reset (H_RST): Setting this bit to 1 will initiate a
HECI reset sequence to get the circular buffers into a
known good state for host and ME communication. When
this bit transitions from 0 to 1, hardware will clear the
H_RDY and ME_RDY bits.
Host Ready (H_RDY): This bit indicates that the host is
ready to process messages.
Datasheet
345