AC82G41SLGQ3 Datasheet, PDF (252/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.31 MA—Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
94–97h
00000000h
RO, RW
32 bits
Bit
31:2
1:0
Access
RW
RO
Default
Value
0000000
0h
00b
RST/
PWR
Core
Core
Description
Message Address (MA): Used by system software to assign an MSI
address to the device. The device handles an MSI by writing the
padded contents of the MD register to this address.
Force DWord Align (FDWA): Hardwired to 0 so that addresses
assigned by system software are always aligned on a DWord address
boundary.
8.32
MD—Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
98–99h
0000h
RW
16 bits
Bit
15:0
Access
RW
Default
Value
0000h
RST/
PWR
Core
Description
Message Data (MD): Base message data pattern assigned by
system software and used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit
value to the memory address specified in the MA register. The upper
16-bits are always set to 0. The lower 16-bits are supplied by this
register.
8.33
PE_CAPL—PCI Express* Capability List
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
A0–A1h
0010h
RO
16 bits
This register enumerates the PCI Express capability structure.
Bit
15:8
7:0
Access
RO
RO
Default
Value
00h
10h
RST/
PWR
Core
Core
Description
Pointer to Next Capability (PNC): This value terminates the
capabilities list. The Virtual Channel capability and any other PCI
Express specific capabilities that are reported via this mechanism are
in a separate capabilities list located entirely within PCI Express
Extended Configuration Space.
Capability ID (CID): Identifies this linked list item (capability
structure) as being for PCI Express registers.
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Datasheet