AC82G41SLGQ3 Datasheet, PDF (371/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.19 IDDHOR0—IDE Drive Head Out Register Device 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
6h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read only by the Host. Host read to this Drive/head In register address
reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=0.
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to 1) in addition to the Host system reset and D3 to
D0 transition of the IDE function.
When the host writes to this address, it updates the value of the IDEDHIR register.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Drive Head Out DEV 0 (IDEDHO0): Drive/Head Out
register of Master device.
Datasheet
371