AC82G41SLGQ3 Datasheet, PDF (238/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.12
IOBASE1—I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
1Ch
F0h
RO, RW
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
Bit
Access
Default
Value
RST/
PWR
Description
7:4
RW
3:0
RO
Fh
Core
I/O Address Base (IOBASE): This field corresponds to A[15:12] of
the I/O addresses passed by bridge 1 to PCI Express.
0h
Core Reserved
8.13
IOLIMIT1—I/O Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
1Dh
00h
RW, RO
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
Bit
Access
Default
Value
RST/
PWR
Description
7:4
RW
3:0
RO
I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O
0h
Core
address limit of device #6. Devices between this upper limit and
IOBASE1 will be passed to the PCI Express hierarchy associated with
this device.
0h
Core Reserved
238
Datasheet