AC82G41SLGQ3 Datasheet, PDF (149/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.27
C1ODTCTRL—Channel 1 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
69C-69Fh
00000000h
R/W, RO
32 bits
Bit
31:12
Access
RO
11:8
R/W
7:4
R/W
3:0
R/W
Default
Value
00000h
0h
0h
0h
RST/PWR
Description
Core
Core
Core
Core
Reserved
DRAM ODT for Read Commands
(sd1_cr_odt_duration_rd): This field specifies the
duration in memory clocks to assert DRAM ODT for Read
Commands. The Async value should be used when the
Dynamic Powerdown bit is set; otherwise use the Sync
value.
DRAM ODT for Write Commands
(sd1_cr_odt_duration_wr): This field specifies the
duration in memory clocks to assert DRAM ODT for Write
Commands. The Async value should be used when the
Dynamic Powerdown bit is set; otherwise, use the Sync
value.
MCH ODT for Read Commands
(sd1_cr_mchodt_duration): This field specifies the
duration in memory clocks to assert (G)MCH ODT for Read
Commands.
5.2.28
EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A00-A01h
0000h
R/W, RO
16 bits
Bit
15:10
9:0
Access
RO
R/W
Default
Value
000000b
000h
RST/
PWR
Core
Core
Description
Reserved
Channel 0 Dram Rank Boundary Address 0
(C0DRBA0):
Datasheet
149