AC82G41SLGQ3 Datasheet, PDF (237/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
19h
00h
RW
8 bits
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge. This number is programmed by the PCI configuration software to allow mapping
of configuration cycles to PCI Express.
Bit
Access
Default
Value
RST/
PWR
Description
7:0
RW
00h
Core
Secondary Bus Number (BUSN): This field is programmed by
configuration software with the bus number assigned to PCI Express.
8.11
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
1Ah
00h
RW
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express.
Bit
Access
Default
Value
RST/
PWR
Description
7:0
RW
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus
00h
Core that lies behind the device #6 bridge. When only a single PCI device
resides on the PCI Express segment, this register will contain the
same value as the SBUSN1 register.
Datasheet
237