AC82G41SLGQ3 Datasheet, PDF (168/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.49
PMSTS—Power Management Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
F14-F17h
00000000h
R/WC/S, RO
32 bits
This register is Reset by PWROK only.
Bit
31:9
8
7:2
1
0
Access
RO
R/WC/S
RO
R/WC/S
R/WC/S
Default
Value
000000h
0b
00h
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
Warm Reset Occurred (WRO): Set by the PMunit
whenever a Warm Reset is received, and cleared by
PWROK=0.
0 = No Warm Reset occurred.
1 = Warm Reset occurred.
BIOS Requirement: BIOS can check and clear this bit
whenever executing POST code. This way BIOS knows that
if the bit is set, then the PMSTS bits [1:0] must also be set,
and if not BIOS needs to power-cycle the platform.
Reserved
Channel 1 in Self-Refresh (C1SR): Set by power
management hardware after Channel 1 is placed in self
refresh as a result of a Power State or a Reset Warn
sequence.
Cleared by Power management hardware before starting
Channel 1 self refresh exit sequence initiated by a power
management exit.
Cleared by the BIOS by writing a 1 in a warm reset
(Reset# asserted while PWROK is asserted) exit sequence.
0 = Channel 1 not ensured to be in self refresh.
1 = Channel 1 in Self Refresh.
Channel 0 in Self-Refresh (C0SR): Set by power
management hardware after Channel 0 is placed in self
refresh as a result of a Power State or a Reset Warn
sequence.
Cleared by Power management hardware before starting
Channel 0 self refresh exit sequence initiated by a power
management exit.
Cleared by the BIOS by writing a 1 in a warm reset
(Reset# asserted while PWROK is asserted) exit sequence.
0 = Channel 0 not ensured to be in self refresh.
1 = Channel 0 in Self Refresh.
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Datasheet