AC82G41SLGQ3 Datasheet, PDF (119/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
15:13
12
Access
RO
R/WC/S
11
R/WC/S
10
RO
9
R/WC/S
8
RO
7
R/WC/S
6:2
RO
1
R/WC/S
0
R/WC/S
Default
Value
000b
0b
0b
0b
0b
0b
0b
00h
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
(G)MCH Software Generated Event for SMI
(GSGESMI): This indicates the source of the SMI was a
Device 2 Software Event.
(G)MCH Thermal Sensor Event for SMI/SCI/SERR
(GTSE): This bit indicates that a (G)MCH Thermal Sensor
trip has occurred and an SMI, SCI, or SERR has been
generated. The status bit is set only if a message is sent
based on Thermal event enables in Error command, SMI
command and SCI command registers. A trip point can
generate one of SMI, SCI, or SERR interrupts (two or more
per event is invalid). Multiple trip points can generate the
same interrupt, if software chooses this mode, subsequent
trips may be lost. If this bit is already set, then an interrupt
message will not be sent on a new thermal sensor event.
Reserved
LOCK to non-DRAM Memory Flag (LCKF): When this bit
is set to 1, the (G)MCH has detected a lock operation to
memory space that did not map into DRAM.
Received Refresh Timeout Flag (RRTOF): Reserved
DRAM Throttle Flag (DTF):
1 = Indicates that a DRAM Throttling condition occurred.
0 = Software has cleared this flag since the most recent
throttling event.
Reserved
Multiple-bit DRAM ECC Error Flag (DMERR): If this bit
is set to 1, a memory read data transfer had an
uncorrectable multiple-bit error. When this bit is set the
address, channel number, and device number that caused
the error are logged in the DEAP register. Once this bit is
set, the DEAP, DERRSYN, and DERRDST fields are locked
until the processor clears this bit by writing a 1. Software
uses bits [1:0] to detect whether the logged error address
is for Single or Multiple-bit error. This bit is reset on
PWROK.
Single-bit DRAM ECC Error Flag (DSERR): If this bit is
set to 1, a memory read data transfer had a single-bit
correctable error and the corrected data was sent for the
access. When this bit is set, the address and device
number that caused the error are logged in the DEAP
register. Once this bit is set, the DEAP, DERRSYN, and
DERRDST fields are locked to further single bit error
updates until the processor clears this bit by writing a 1. A
multiple bit error that occurs after this bit is set will
overwrite the DEAP and DERRSYN fields with the multiple-
bit error signature and the DMERR bit will also be set. A
single bit error that occurs after a multi-bit error will set
this bit but will not overwrite the other fields. This bit is
reset on PWROK.
Datasheet
119