AC82G41SLGQ3 Datasheet, PDF (413/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.3
TXT.THREAD.EXISTS—TXT Thread Exists Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
10-17h
0000000000000000h
RO
64 bits
This register is used to read which threads are registered as TXT capable
Bit
63:32
31:0
Access
Default
Value
Description
TXT Threads Exists (Reserved) (TXT.THRDS.EXISTS_R): This bit field
indicates the threads on the FSB that have issued a cycle. The bit is set based on
any processor cycle initiated by the thread after reset. The GETSEC instruction is
expected to be performed after each thread has performed at least one cycle.
When the chipset detects the presence of a particular thread, it sets the
corresponding bit in this register.
This register is locked when SENTER is seen on the FSB.
The following bit mapping is used:
RO
0000000 _Bits
0h
7:0
Usage
CPU #0, threads # 1-4
15:8 CPU #1, threads # 1-4
23:16 CPU #2, threads # 1-4
31:24 CPU #3, threads # 1-4
63:32 Reserved
NOTES:The processor is defined by the Defer ID bits, DID[6:5]. The thread is
defined by ATTR[6:5]. At the moment that defines only 4 processor's and
4 threads. The other bits are reserved for future changes.
TXT Thread Exists (TXT.THRDS.EXISTS): This bit field indicates the threads
on the FSB that have issued a cycle. The bit is set based on any processor cycle
initiated by the thread after reset. The GETSEC instruction is expected to be
performed after each thread has performed at least one cycle. When the chipset
detects the presence of a particular thread, it sets the corresponding bit in this
register.
This register is locked when SENTER is seen on the FSB.
The following bit mapping is used:
RO
0000000 _Bits
0h
7:0
Usage
CPU #0, threads # 1-4
15:8 CPU #1, threads # 1-4
23:16 CPU #2, threads # 1-4
31:24 CPU #3, threads # 1-4
63:32 Reserved
NOTE: The CPU is defined by the Defer ID bits, DID[6:5]. The thread is defined
by ATTR[6:5]. At the moment that defines only 4 processors and 4
threads. The other bits are reserved for future changes.
Datasheet
413