AC82G41SLGQ3 Datasheet, PDF (289/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
Graphics Mode Select (GMS): This field is used to select the
amount of Main Memory that is pre-allocated to support the Internal
Graphics device in VGA (non-linear) and Native (linear) modes. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
0000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA
cycles (Memory and I/O), and the Sub-Class Code field within Device
2, Function 0 Class Code register is 80h.
0001 = Reserved
0010 =Reserved
0011 =Reserved
0100 =Reserved
0101 =DVMT (UMA) mode, 32 MB of memory pre-allocated for frame
buffer.
0110 =DVMT (UMA) mode, 48 MB of memory pre-allocated for frame
buffer.
0111 =DVMT (UMA) mode, 64 MB of memory pre-allocated for frame
7:4
RO
0011b Core
buffer.
1000 =DVMT (UMA) mode, 128 MB of memory pre-allocated for
frame buffer.
1001 =DVMT (UMA) mode, 256 MB of memory pre-allocated for
frame buffer.
1010 =DVMT (UMA) mode, 96 MB of memory pre-allocated (0 + 96).
1011 =DVMT (UMA) mode, 160 MB of memory pre-allocated (64 +
96).
1100 =DVMT (UMA) mode, 224 MB of memory pre-allocated (128 +
96).
1101 =DVMT (UMA) mode, 352 MB of memory pre-allocated (256 +
96).
NOTE: This register is locked and becomes Read Only when the
D_LCK bit in the SMRAM register is set.
Hardware does not clear or set any of these bits automatically based
on IGD being disabled/enabled.
BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1
of this register) is 0.
3:2
RO
00b
Core Reserved
IGD VGA Disable (IVD):
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the
Sub-Class Code within Device 2 Class Code register is 00h.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub- Class Code field within Device 2 function 0
1
RO
0b
Core
Class Code register is 80h.
BIOS Requirement: BIOS must not set this bit to 0 if the GMS field
(bits 6:4 of this register) pre-allocates no memory. This bit MUST be
set to 1 if Device 2 is disabled either via a fuse or fuse override
(CAPID0[38] = 1) or via a register (DEVEN[3] = 0).
0
RO
0b
Core Reserved
Datasheet
289