AC82G41SLGQ3 Datasheet, PDF (246/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
34h
88h
RO
8 bits
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Bit
Access
Default
Value
RST/
PWR
Description
7:0
RO
88h
Core
First Capability (CAPPTR1): The first capability in the list is the
Subsystem ID and Subsystem Vendor ID Capability.
8.22
INTRLINE1—Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
3Ch
00h
RW
8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Bit
Access
Default
Value
RST/
PWR
Description
7:0
RW
00h
Core
Interrupt Connection (INTCON): Used to communicate interrupt
line routing information.
8.23
INTRPIN1—Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
3Dh
01h
RO
8 bits
This register specifies which interrupt pin this device uses.
Bit
Access
Default
Value
RST/
PWR
Description
7:0
RO
01h
Core
Interrupt Pin (INTPIN): As a single function device, the PCI
Express device specifies INTA as its interrupt pin. 01h=INTA.
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Datasheet